RPI Electronics Club
Seminar/Workshop
DIGITAL ELECTRONICS
Logic Basics:
Common digital electronics use only 2 voltage levels:
· 5v = 1, High, Hi, On, Asserted
· 0v = 0, Low, Lo, Off, Unasserted
· Anything else is invalid
There are two main logic families:
· TTL (Transistor-Transistor Logic)
Integrated Circuits labeled like 74HCT00
· CMOS (Complimentary Metal-Oxide Semiconductor)
Integrated Circuits labeled like CD4017 or MC14521
Integrated Circuit considerations:
· Pin#1 is denoted by a small dimple, and is to the left of a notch.
· The last pin on the Left side is usually Vss (Ground, 0v).
·
The last pin on the Right side is usually Vcc or Vdd (Supply, 5v).
· For all other data, refer to the TTL or CMOS Data Book.
Logic Gates:
Not Gate (Inverter) - The output is the inverse of the input
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Ex. 74LS04 and CD4049
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And Gate |
Nand Gate |
Or Gate |
Nor Gate |
Xor Gate |
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Truth Table:
Ex. 74HC08 CD4081 |
Truth Table:
Ex. 74HCT00 CD4011 |
Truth Table:
Ex. 74F32 CD4071 |
Truth Table:
Ex. 74AC02 CD4001 |
Truth Table:
Ex. 74LS136 |
Logic Gates can also have more than 2 inputs.
·
For instance, the 4-Input Or gate has a low output
only when all inputs are low.
Schmitt
Trigger Inputs:
· Normal inputs accept only 0v or 5v, and nothing in between.
· Schmitt Trigger Inputs will translate an analog voltage from 0-5v into an acceptable logic level. For instance, 1.34v would become 0v, and 3.4v would become 5v.
· Schmitt trigger inputs are available on nearly all logic gates.
Special Function ICs:
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Counters / Dividers |
BCD Converters |
Latches / Flip-Flops |
Shift Registers |
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Decimal Counter
Binary Counter |
BCD to 7-Segment
BCD to Decimal |
D Flip-Flop
-A clock transition on CP transfers the input at D to the output Q. Otherwise, Q retains its previous state. SR Latch
-A 1 at R (reset) sets Q to 0. A 1 at S (set) sets Q to 1. A 0 at both S and R leaves Q at its previous state. |
Serial in Parallel Out
-The serial data applied to D gets shifted from Q0 to Q3 based on the clock applied to CP. Parallel in Serial Out
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As with the logic gates, a bubble on a pin or a line over a name means an inversion. Also,
CP = Clock Pulse CE = Chip Enable
A or D = Input Q = Output
MR,
CLR = Master
For Information on these and other chips, see the TTL or CMOS Databook.
Other Considerations:
Pull-up Resistors:
· Needed on Open Collector ICs, and wherever the logic voltage may “float”.
· The resistor “pulls” the output up to a logic “High” if it is left floating.
Decoupling Capacitors:
· For “good” logic design connect a 0.1 uF capacitor across each IC’s power pins.
· This eliminates noise from entering the IC and causing false triggering.
De-bouncing:
· Manual switches tend to “bounce” when switched, causing multiple pulses per switching action.
· Bouncing can be corrected Using a special De-Bouncing circuit, Software correction in a microcontroller, or sometimes a capacitor from the input to ground (2.2uF sometimes works).
Clock Sources:
· Most digital designs rely on a
constant pulse train, or Clock.
· TTL
· 555 Timer – 8 pin IC used in Astable Oscillator mode. Please reference the datasheet for more information.
Logic Probe and Pulser:
Logic probe: Used to probe the logic level at any point in a circuit.
· Connect the alligator clips Red to +5 and Black to Ground. The tip is the probe.
Logic Pulser: Used to temporarily pulse (clock) a circuit so as to view the result.
· Connect the alligator clips Red to +5 and Black to Ground. The tip is provides the pulses.
Basic Binary Counter Circuit:
· The 4 LEDs display a binary number which increments at the push of a button.
· S1 Serves as the Clock Pulse to increment the counter. Depending on the type of switch used, S1 may require de-bouncing. S2 Serves as a Reset button.
· Notice the pull-up and pull-down resistors on the inputs, to prevent “floating”.
